The increasing power of computing systems has resulted in the drive for memory devices of increased size and speed. At the same time, in order to manufacture such devices with increased efficiency, it is desirable to make the physical size of such memory devices as small as possible. Therefore, it is always desirable to find some way of increasing the data density (the amount of data that can be stored in a given area) of a semiconductor memory device. This holds true for "embedded" memory applications as well. Embedded applications include a memory array as but one portion of a semiconductor device that provides higher functionality. If an embedded memory core can be reduced in size, more area can be dedicated to other circuits, or the overall physical size of the device can be reduced.
Any way of reducing the physical size of a semiconductor memory device can translate directly into considerable cost savings in the manufacture of the device. Furthermore, because the majority of the area in a memory device is occupied by memory storage cells, any way of reducing the area required for a memory cells will greatly contribute to reducing the overall size of a memory device.
Memory devices are typically manufactured by depositing and patterning a series of fabrication layers. Such layers include alternating conductive and insulating layers. Each fabrication layer is usually patterned using a lithography and etch step. The lithography step involves depositing a layer of photoresist over a layer and then "developing" or "printing" a pattern within the photoresist. The pattern is typically developed by selectively exposing portions of the photoresist to some sort of radiation. The most common form of radiation, due to its cost effectiveness, is light. To generate the pattern, a photomask containing the desired pattern is situated over the photoresist, and then light is shone through the photomask to develop the pattern within the photoresist. The undeveloped portions of the photoresist are removed with a solvent, leaving the developed pattern.
The developed pattern of photoresist will then serve as an etch mask for the fabrication layer below. An etch is applied and those portions of the fabrication layer that are exposed to the etch, are removed. Those portions of the fabrication layer that are situated below the developed photoresist pattern, will be protected from the etch, and hence remain intact. In this manner structures or "features" are formed in the fabrication layer by the etch step. For example, in the event the fabrication layer is a conductive layer, the etch step can create conductive interconnects between various portions of a device. In the event the fabrication layer is an insulating layer, the etch step can create contact holes through the insulating layer to a conductive layer below. In order to reduce the overall size of a semiconductor device, efforts are continually made to create structures that have the smallest feature sizes possible. Thus, it is desirable to print photoresist patterns as small as possible with as much reliability as possible.
Feature sizes also dictate how close structures can be situated relative to one another in a semiconductor device. This limitation arises due to avoidable misalignment errors between subsequent photomasks. For example, the minimum feature size is typically given by the variable "F." In some devices, certain structures may have to be separated from one another by distance F, to ensure the device will operate properly. For example, a contact hole created by one photomask may have to be separated from an adjacent conductive line, created by a previous photomask, by the distance F. This ensures that the misalignment between the conductive line and the contact hole will not result in the contact hole exposing, and thereby creating a short to, the conductive line.
Because the variable F dictates the minimum size and separation of various structures, it is common to describe the size of device units in terms of F. For example, in some types of semiconductor memory devices, such as dynamic random access memories (DRAMs) or ferroelectric memories, memory cell area is often described in terms of the value F. In the case of such memory devices having a "folded" bit line architecture, the smallest size memory cell area is believed to be 8F.sup.2. In the case of such memory devices having "open" bit line architectures, the smallest memory cell size area is believed to be 6F.sup.2.
In addition to impacting the overall size of a semiconductor device, feature sizes also play an important part in the functionality of a semiconductor device. For example, in order to create accurate etch mask patterns from a layer of photoresist, sufficient light intensity must be applied to the photoresist to print the pattern. However, as photomasks are made for devices having increasingly smaller features sizes, it becomes more and more difficult to provide sufficient light intensity through the openings. For example, a common minimum feature size object in a semiconductor device is a contact hole. The small photomask opening used to create the contact hole may not allow enough light intensity to create an accurate etch mask. Such limitations on contact formation can produce a barrier to further decreasing the size of a semiconductor device, particularly those devices having a high number of contacts, such as DRAMs and ferroelectric memories.
While advanced lithography methods, such as electron beam lithography, can be used to create smaller feature sizes, such approaches can be more complex, require expensive equipment, and take more time than light-based lithography approaches.
Referring now to FIG. 1, a prior art open bit line DRAM array architecture is set forth. The array architecture is designated by the general reference character 100 and includes a number of memory cells, each having a 6F.sup.2 cell area. The top plan view is shown with portions of various structures removed to better understand their arrangement with one another. The array architecture 100 includes a number of active areas 102a-102o or "moats" formed within a monocrystalline semiconductor substrate, and separated from one another by an isolation structure 104. A number of word lines 106a-106d are arranged over the active areas 102a-102o, with two word lines being formed over each of the active areas. The word lines form the control gates for two pass transistors within each of the active areas 102a-102o. The word lines to the right of word line 106d are not shown to better illustrate the structures underneath.
In the view of FIG. 1, the horizontal direction can be considered the column direction, and the vertical direction can be considered the row direction. Thus, the active areas 102a-102o can be considered to belong to different columns within the array. For example, active areas 102d-102f are in one column, and active areas 102g-102i are in an adjacent column.
Following the deposition of one or more insulating layers, a number of bit line contacts 108a-108j are formed by a lithography and etch step. The deposition of a conductive layer is performed afterward. One bit line contact is formed to each of the active areas 102a-102o. The bit line contacts 108a-108j are ideally formed offset with respect to their respective active areas 108a-108j. For example, bit line contact 108e is shown to have a lower portion overlapping active area 102f and an upper portion overlapping that portion of the isolation structure 104 that separates active area 102f from active area 102c. Each bit line contact 108a-108j is coupled to a region that serves as a common source for the two pass transistors of its respective active area. In order to illustrate the shape of active area 102h, the bit line contact that would be connected to active area 102h is not shown in FIG. 1.
In the prior art array architecture 100, a number of bit lines 110a-110e are ideally formed over the existing structures, making contact with the bit line contacts 108a-108j. The bit lines 110a-110e are arranged generally perpendicular to the word lines 106a-106d and between the active areas 102a-102o. While bit line 110a is shown extending across the full length of the portion of the array architecture 100, right portions of the bit lines 110b-110e are not shown to illustrate the structures beneath.
The array architecture 100 further includes a collection of storage node contacts, shown as 112a-112x. The storage node contacts 112a-112x are coupled to the drains of the pass transistors formed within the active areas 102a-102o. Storage capacitors (not shown in FIG. 1) can be formed, with one being coupled to each of the storage node contacts 112a-112x.
In the array architecture 100 of FIG. 1, the minimum width of the active areas 102a-102o, and the minimum width of the isolation structure 104 between adjacent active areas is the minimum feature size, F. Furthermore, the minimum width of the word lines 106a-106d is also the minimum feature size F. The area of one memory cell is shown in FIG. 1 by the dashed line 114. Taking into consideration the feature sizes noted, the memory cells are shown to have an area equal to 6F.sup.2, as noted above.
While the array architecture 100 of FIG. 1 provides for a compact memory cell array, a drawback to the architecture is the strict alignment requirements for the bit line contacts 108a-108j with respect to the active areas 102a-102o. This alignment requirement is best understood with reference to FIG. 2. FIG. 2 is a top plan view illustrating a first active area 200a, a second active area 200b, a bit line contact 202, a first bit line 204a, and an adjacent second bit line 202b. The minimum feature size is shown as "F" in FIG. 2. In the arrangement of FIG. 2, it is intended that bit line contact 202 connect the active area 200b to the first bit line 204a.
In order to ensure that the bit line contact 202 is not erroneously connected to the active area 200a (as opposed to the intended active area 200b) a minimum distance must be maintained between the bit line contact 202 and the active area 200a. This distance is shown as d in FIG. 2. At the same time, the bit line 204a must be sufficiently far from the adjacent bit line 204b, to avoid making contact with it. The bit line contact 202 in FIG. 2, thus shows the resulting allowable range of the bit line contact. The distance d distance will be less than 1/2 F. Such spacing does not provide enough margin for misalignment errors, and so is not suitable for conventional manufacturing processes. Thus, the manufacturability of the 6F.sup.2 cell memory array set forth in FIGS. 1 and 2 is impractical.
It would be desirable to arrive at a memory array architecture having memory cells with a 6F.sup.2 area that do not suffer from the alignment constraints of the prior art.